Automatic Test Equipment (ATE) is commonly used within the field of electronic chip manufacturing for the purposes of testing electronic components. ATE systems both reduce the amount of time spent on testing devices to ensure that the device functions as designed and serve as a diagnostic tool to determine the presence of faulty components within a given device before it reaches the consumer.
ATE systems can perform a number of test functions on a device under test (DUT) through the use of test signals transmitted to and from the DUT. Conventional ATE systems are very complex electronic systems and generally include printed circuit boards (PCB), coax cables and waveguides to extend the signal path of test signals transmitted from the DUT to a tester diagnostic system during a test session. However, increases to the length of the signal path, particularly at millimeter frequencies, can result in substantial loss of signal strength which can degrade the integrity of test signals transmitted from the DUT at high frequencies.
Conventional ATE systems use PCBs that include several centimeters of microstrip transmission lines disposed on the surface of a PCB to convey test signals from a DUT to a tester diagnostic system. Accordingly, the elongation of the test signal path caused by use of longer microstrip transmission lines as well as other components, such as coax cables by modern ATE systems can result in unnecessary signal loss at high frequencies.
FIG. 1 illustrates an exemplary interface assembly for testing DUTs. Typically the DUT 102 is inserted into a socket 101 affixed to a PCB 105, wherein the DUT communicates to the tester (ATE source 110 or ATE receiver 111) through the PCB 105 and the waveguide assembly 120. The socket 101 is a physical device having connectors for electrically interfacing with IO pins (e.g. solder ball 102) of the DUT. Manufacturers of the DUTs and test engineers testing the DUTs typically need to know the electrical characteristics of the socket interface with respect to the tester in order to accurately test the device especially at high frequencies.
For example, if the DUT is producing power, a test engineer would need to know how much power is being produced right at the DUT IO pin 180 that is then transmitted through channel 192 before being received at the ATE receiver 111. Typically, the power will attenuate as the signal transmits along path 192, therefore, it would be important for the test engineer to know the power being produced right at the IO pin of the DUT in order to perform a more accurate calibration. Similarly, if the DUT receives power from the ATE source 110 through channel 191 at IO pin 102, a test engineer would need to know precisely how much power is being received at IO pin 102 in order to perform a more precise calibration.
However, conventional methodologies of determining the electrical characteristics of the socket and performing power calibration for the socket are deficient because they are either prohibitively expensive or impractical.
FIG. 2 illustrates an exemplary methodology for performing socket power calibration that is conventional. FIG. 2 illustrates a sandwich style socket calibration device, wherein an elastomer layer is sandwiched between two PCB boards. The upper PCB 202 stimulates the DUT and contains a cable connector that can be connected to a network analyzer for measuring the electrical characteristics of the socket layer 205 which is sandwiched between the PCB boards. The lower PCB 204 can be connected to a tester system via another cable connector. Typically, 1 mm cable connectors 210 are used to interface to the network analyzer (and tester) and are placed on the PCBs. Traces on the PCBs couple the cable connectors to the socket ports.
The methodology illustrated in FIG. 2, while functional, has several drawbacks. First, it typically uses a high frequency (e.g. 110 GHz) network analyzer which can be prohibitively expensive and is highly specialized and complex requiring a highly skilled engineer to set up and deploy. Thus, the methodology of FIG. 2 is not practical for use in a production testing floor with lower skilled technicians. Further, not only is the network analyzer itself expensive, but the 1 mm cable connectors and other elements needed for this methodology are also extremely costly. Further, since the PCBs are rigid, they limit the orientation of the device with respect to the tester. In other words, it may be difficult to physically interface the network analyzer with the ports on the DUT because a bottom-only mounting position is available. Finally, the long PCB traces introduce loss and, further, the design is only single ended. As a result, conventional methods of performing power socket calibration are impractical and cost-prohibitive.